feat: 添加GD32E508 DCU应用工程的初始结构

- 新增完整的CMSIS解决方案配置，包含AC6/GCC/IAR/CLANG编译器支持
- 添加项目配置文件，定义了设备层、系统层、应用层的模块结构
- 配置ARM::CMSIS和GigaDevice::GD32E50x_DFP软件包依赖
- 创建多层代码架构：应用入口(main)、系统层(sys)、设备层(device)
- 实现任务管理系统，包含任务调度器和任务执行器分离设计
- 集成ADC、CANFD、定时器、串口、温度采样等核心功能模块
- 添加详细的README文档说明项目结构和代码组织方式
- 配置AC6链接脚本和运行时环境文件
- 设置Git忽略规则以排除编译产物和临时文件

GD32E508_DCU_APP/RTE/Device/GD32E508VE/regions_GD32E508VE.h

@@ -0,0 +1,101 @@
+#ifndef REGIONS_GD32E508VE_H
+#define REGIONS_GD32E508VE_H
+
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+//------ With VS Code: Open Preview for Configuration Wizard -------------------
+
+// <n> Auto-generated using information from packs
+// <i> Device Family Pack (DFP):   GigaDevice::GD32E50x_DFP@1.9.0
+
+// <h> ROM Configuration
+// =======================
+// <h> __ROM0 (is rx memory: IROM1 from DFP)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region. Default: 0x08000000
+//   <i> Contains Startup and Vector Table
+#define __ROM0_BASE 0x08000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region. Default: 0x00080000
+#define __ROM0_SIZE 0x00080000
+// </h>
+
+// <h> __ROM1 (unused)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+#define __ROM1_BASE 0x0
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+#define __ROM1_SIZE 0x0
+// </h>
+
+// <h> __ROM2 (unused)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+#define __ROM2_BASE 0x0
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+#define __ROM2_SIZE 0x0
+// </h>
+
+// <h> __ROM3 (unused)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+#define __ROM3_BASE 0x0
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+#define __ROM3_SIZE 0x0
+// </h>
+
+// </h>
+
+// <h> RAM Configuration
+// =======================
+// <h> __RAM0 (is rwx memory: IRAM1 from DFP)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region. Default: 0x20000000
+//   <i> Contains uninitialized RAM, Stack, and Heap
+#define __RAM0_BASE 0x20000000
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region. Default: 0x00020000
+#define __RAM0_SIZE 0x00020000
+// </h>
+
+// <h> __RAM1 (unused)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+#define __RAM1_BASE 0x0
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+#define __RAM1_SIZE 0x0
+// </h>
+
+// <h> __RAM2 (unused)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+#define __RAM2_BASE 0x0
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+#define __RAM2_SIZE 0x0
+// </h>
+
+// <h> __RAM3 (unused)
+//   <o> Base address <0x0-0xFFFFFFFF:8>
+//   <i> Defines base address of memory region.
+#define __RAM3_BASE 0x0
+//   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
+//   <i> Defines size of memory region.
+#define __RAM3_SIZE 0x0
+// </h>
+
+// </h>
+
+// <h> Stack / Heap Configuration
+//   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+#define __STACK_SIZE 0x00000200
+#define __HEAP_SIZE 0x00000C00
+// </h>
+
+
+#endif /* REGIONS_GD32E508VE_H */