cbb/DCU_APP
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat(canfd): 添加CANFD自检功能和桥接模式支持

Browse Source 
- 添加完整的CANFD初始化流程，包括硬复位机制解决CAN1卡死问题
- 实现CANFD自检功能，包含物理总线测试和内部回环测试
- 支持CAN0到CAN1/CAN2的透传桥接模式
- 添加详细的初始化诊断信息输出
- 修复CAN滤波器配置和GPIO映射问题
- 增强错误处理和状态监控功能

perf(system): 优化系统时钟配置提高性能

- 将AHB时钟从SYSCLK/4调整为SYSCLK/2 (60MHz)
- 优化PLL预分频配置参数
- 更新相关时序注释以反映实际频率变化

docs(esc): 更新EXMC总线时序配置注释

- 添加LAN9252 HBI时序要求详细说明
- 注明当前ESC未启用状态下的占位符说明
- 提供实际计算得出的HCLK延迟要求
This commit is contained in:
cbb
2026-07-02 02:02:41 +08:00
parent b171767023
commit 6aa21a1f9d
11 changed files with 608 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files
GD32E508_DCU_APP/RTE/Device/GD32E508VE/system_gd32e50x.c
+10 -10
View File
@@ -1,4 +1,4 @@
/*!
/*!
\file system_gd32e50x.c
\brief CMSIS Cortex-M33 Device Peripheral Access Layer Source File for
GD32E50x Device Series
@@ -850,11 +850,11 @@ static void system_clock_120m_hxtal(void)
RCU_APB1EN |= RCU_APB1EN_PMUEN;
/* HXTAL is stable */
/* AHB = SYSCLK/4 */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV4;
/* APB2 = AHB/1 */
/* AHB = SYSCLK/2 (60 MHz) */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV2;
/* APB2 = AHB/1 (60 MHz) */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
/* APB1 = AHB/2 (30 MHz) */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
#if defined(GD32E50X_HD)
@@ -867,13 +867,13 @@ static void system_clock_120m_hxtal(void)
RCU_CFG0 |= RCU_PLL_MUL30;
#elif (defined(GD32E50X_CL) || defined(GD32E508))
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
/* CK_PREDIV0 = (CK_HXTAL)/2 *8 /8 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV5 | RCU_PREDV0_DIV10);
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV8);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
@@ -882,11 +882,11 @@ static void system_clock_120m_hxtal(void)
}
#elif defined(GD32EPRT)
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
/* CK_PREDIV0 = (CK_HXTAL)/2 *8 /8 = 4 MHz */
/* CK_PREDIV0 = (CK_HXTAL)/2 *8 /8 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV8);