feat(core): OTA可用版本，添加看门狗功能并优化系统初始化日志
- 添加watchdog组件用于系统监控 - 在system_gd32e50x.c中增加USART0诊断输出，在IRC8M和PLL配置后 发送"APP"和"CLK"标识 - 优化AppSpiCommand类中的日志处理机制，使用临界区保护 - 添加对全0xFF数据包的过滤处理，避免无效命令处理 - 将OTA重启延时从滴答计数改为毫秒级延时，提高响应速度 - 移除温度传感器相关文件，添加看门狗相关文件到项目配置 - 更新FWDGT API调用方式，使用新的配置函数 - 增加详细的启动日志输出，便于调试和追踪初始化过程
This commit is contained in:
@@ -0,0 +1,227 @@
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/*!
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\file gd32e50x_fwdgt.c
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\brief FWDGT driver
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\version 2026-02-09, V1.7.0, firmware for GD32E50x
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
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||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32e50x_fwdgt.h"
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/*!
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\brief enable write access to FWDGT_PSC and FWDGT_RLD
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fwdgt_write_enable(void)
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{
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FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
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}
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/*!
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\brief disable write access to FWDGT_PSC and FWDGT_RLD
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fwdgt_write_disable(void)
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{
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FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
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}
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/*!
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\brief start the free watchdog timer counter
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fwdgt_enable(void)
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{
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FWDGT_CTL = FWDGT_KEY_ENABLE;
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}
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/*!
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\brief configure the free watchdog timer counter prescaler value
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\param[in] prescaler_value: specify prescaler value
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only one parameter can be selected which is shown as below:
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\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
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\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
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\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
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\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
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\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
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\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
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\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
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{
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uint32_t timeout = FWDGT_PSC_TIMEOUT;
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uint32_t flag_status = RESET;
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ErrStatus status = SUCCESS;
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/* enable write access to FWDGT_PSC */
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FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
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/* configure FWDGT */
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FWDGT_PSC = (uint32_t)prescaler_value;
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/* wait until the PUD flag to be reset */
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do {
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flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
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} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
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if((uint32_t)RESET != flag_status) {
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status = ERROR;
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}
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return status;
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}
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/*!
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\brief configure the free watchdog timer counter reload value
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\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
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{
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uint32_t timeout = FWDGT_RLD_TIMEOUT;
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uint32_t flag_status = RESET;
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ErrStatus status = SUCCESS;
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/* enable write access to FWDGT_RLD */
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FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
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/* configure FWDGT_RLD */
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FWDGT_RLD = RLD_RLD(reload_value);
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/* wait until the RUD flag to be reset */
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do {
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flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
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} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
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if((uint32_t)RESET != flag_status) {
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status = ERROR;
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}
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return status;
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}
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/*!
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\brief reload the counter of FWDGT
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fwdgt_counter_reload(void)
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{
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FWDGT_CTL = FWDGT_KEY_RELOAD;
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}
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/*!
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\brief configure counter reload value, and prescaler divider value
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\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
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\param[in] prescaler_value: FWDGT prescaler value
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only one parameter can be selected which is shown as below:
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\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
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\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
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\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
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\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
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\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
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\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
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\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value)
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{
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uint32_t timeout = FWDGT_PSC_TIMEOUT;
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uint32_t flag_status = RESET;
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ErrStatus status = SUCCESS;
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/* start the free watchdog timer counter */
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FWDGT_CTL = FWDGT_KEY_ENABLE;
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/* enable write access to FWDGT_PSC,and FWDGT_RLD */
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FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
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/* configure FWDGT PSC */
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FWDGT_PSC = (uint32_t)prescaler_value;
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/* wait until the PUD flag to be reset */
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do {
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flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
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} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
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if((uint32_t)RESET != flag_status) {
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status = ERROR;
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}
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if(SUCCESS == status) {
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/* configure FWDGT_RLD */
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FWDGT_RLD = RLD_RLD(reload_value);
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/* wait until the RUD flag to be reset */
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timeout = FWDGT_RLD_TIMEOUT;
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do {
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flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
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} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
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if((uint32_t)RESET != flag_status) {
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status = ERROR;
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}
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}
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if(SUCCESS == status) {
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/* reload the counter */
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FWDGT_CTL = FWDGT_KEY_RELOAD;
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}
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return status;
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}
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/*!
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\brief get flag state of FWDGT
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\param[in] flag: flag to get
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only one parameter can be selected which is shown as below:
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\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
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\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus fwdgt_flag_get(uint16_t flag)
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{
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FlagStatus flag_status = RESET;
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if(FWDGT_STAT & flag) {
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flag_status = SET;
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}
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return flag_status;
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}
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@@ -0,0 +1,227 @@
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/*!
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\file gd32e50x_fwdgt.c
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\brief FWDGT driver
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\version 2026-02-09, V1.7.0, firmware for GD32E50x
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
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OF SUCH DAMAGE.
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*/
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#include "gd32e50x_fwdgt.h"
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/*!
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\brief enable write access to FWDGT_PSC and FWDGT_RLD
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fwdgt_write_enable(void)
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{
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FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
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}
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/*!
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\brief disable write access to FWDGT_PSC and FWDGT_RLD
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fwdgt_write_disable(void)
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{
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FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
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}
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/*!
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\brief start the free watchdog timer counter
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fwdgt_enable(void)
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{
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FWDGT_CTL = FWDGT_KEY_ENABLE;
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}
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/*!
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\brief configure the free watchdog timer counter prescaler value
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\param[in] prescaler_value: specify prescaler value
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only one parameter can be selected which is shown as below:
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\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
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\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
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\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
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\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
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\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
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\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
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\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
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\param[out] none
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\retval ErrStatus: ERROR or SUCCESS
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*/
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ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
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{
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uint32_t timeout = FWDGT_PSC_TIMEOUT;
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uint32_t flag_status = RESET;
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ErrStatus status = SUCCESS;
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/* enable write access to FWDGT_PSC */
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FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
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/* configure FWDGT */
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FWDGT_PSC = (uint32_t)prescaler_value;
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/* wait until the PUD flag to be reset */
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do {
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flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
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} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
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if((uint32_t)RESET != flag_status) {
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status = ERROR;
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}
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return status;
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}
|
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|
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/*!
|
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\brief configure the free watchdog timer counter reload value
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\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
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\param[out] none
|
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\retval ErrStatus: ERROR or SUCCESS
|
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*/
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ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
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{
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uint32_t timeout = FWDGT_RLD_TIMEOUT;
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uint32_t flag_status = RESET;
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ErrStatus status = SUCCESS;
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/* enable write access to FWDGT_RLD */
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FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
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/* configure FWDGT_RLD */
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FWDGT_RLD = RLD_RLD(reload_value);
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/* wait until the RUD flag to be reset */
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do {
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flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
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} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
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|
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if((uint32_t)RESET != flag_status) {
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status = ERROR;
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}
|
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|
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return status;
|
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}
|
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|
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/*!
|
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\brief reload the counter of FWDGT
|
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\param[in] none
|
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\param[out] none
|
||||
\retval none
|
||||
*/
|
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void fwdgt_counter_reload(void)
|
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{
|
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FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
/*!
|
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\brief configure counter reload value, and prescaler divider value
|
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\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[in] prescaler_value: FWDGT prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
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\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
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\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
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\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
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\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
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\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
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\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
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\param[out] none
|
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\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value)
|
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{
|
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uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
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uint32_t flag_status = RESET;
|
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ErrStatus status = SUCCESS;
|
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|
||||
/* start the free watchdog timer counter */
|
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FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||
|
||||
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* configure FWDGT PSC */
|
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FWDGT_PSC = (uint32_t)prescaler_value;
|
||||
|
||||
/* wait until the PUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
if(SUCCESS == status) {
|
||||
/* configure FWDGT_RLD */
|
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FWDGT_RLD = RLD_RLD(reload_value);
|
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|
||||
/* wait until the RUD flag to be reset */
|
||||
timeout = FWDGT_RLD_TIMEOUT;
|
||||
do {
|
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flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
status = ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
if(SUCCESS == status) {
|
||||
/* reload the counter */
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state of FWDGT
|
||||
\param[in] flag: flag to get
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
|
||||
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||
{
|
||||
FlagStatus flag_status = RESET;
|
||||
if(FWDGT_STAT & flag) {
|
||||
flag_status = SET;
|
||||
}
|
||||
return flag_status;
|
||||
}
|
||||
@@ -1,4 +1,4 @@
|
||||
/*!
|
||||
/*!
|
||||
\file system_gd32e50x.c
|
||||
\brief CMSIS Cortex-M33 Device Peripheral Access Layer Source File for
|
||||
GD32E50x Device Series
|
||||
@@ -162,6 +162,33 @@ static void _soft_delay_(uint32_t time)
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* ===== DIAG: raw USART0 output at IRC8M (8MHz) ===== */
|
||||
/* Enable AFIO + GPIOA + USART0 clocks via raw register */
|
||||
*((volatile uint32_t *)0x40021018U) |= (1U << 14) | (1U << 2) | (1U << 0);
|
||||
/* PA9 = AF_PP, 50MHz (CTL=0b11, MD=0b11) -> CTL1 bit[4..7]=0b1011 */
|
||||
{
|
||||
volatile uint32_t ctl = *((volatile uint32_t *)0x40010804U);
|
||||
ctl &= ~(0xFU << 4);
|
||||
ctl |= (0xBU << 4); /* AF_PP 50MHz */
|
||||
*((volatile uint32_t *)0x40010804U) = ctl;
|
||||
}
|
||||
/* USART0 baud: BAUD = 8000000/115200 = 69 */
|
||||
*((volatile uint32_t *)0x40013808U) = 69U;
|
||||
/* USART0 CTL0: TE + EN = bit3 + bit13 */
|
||||
*((volatile uint32_t *)0x40013800U) = (1U << 3) | (1U << 13);
|
||||
/* Send "APP" via USART0 DATA register */
|
||||
*((volatile uint32_t *)0x40013804U) = 'A';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = 'P';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = 'P';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = '\r';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = '\n';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
/* ===== END DIAG ===== */
|
||||
|
||||
/* FPU settings */
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
@@ -196,6 +223,22 @@ void SystemInit (void)
|
||||
|
||||
/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
|
||||
system_clock_config();
|
||||
|
||||
/* ===== DIAG: after PLL config, at 180MHz, send "CLK" ===== */
|
||||
/* Re-enable USART0 at 180MHz: BAUD = 180000000/115200 = 1562.5 = 1563 */
|
||||
*((volatile uint32_t *)0x40013808U) = 1563U;
|
||||
*((volatile uint32_t *)0x40013800U) = (1U << 3) | (1U << 13);
|
||||
*((volatile uint32_t *)0x40013804U) = 'C';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = 'L';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = 'K';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = '\r';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
*((volatile uint32_t *)0x40013804U) = '\n';
|
||||
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
|
||||
/* ===== END DIAG ===== */
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
|
||||
|
||||
Reference in New Issue
Block a user