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feat(core): OTA可用版本，添加看门狗功能并优化系统初始化日志

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- 添加watchdog组件用于系统监控
- 在system_gd32e50x.c中增加USART0诊断输出，在IRC8M和PLL配置后
  发送"APP"和"CLK"标识
- 优化AppSpiCommand类中的日志处理机制，使用临界区保护
- 添加对全0xFF数据包的过滤处理，避免无效命令处理
- 将OTA重启延时从滴答计数改为毫秒级延时，提高响应速度
- 移除温度传感器相关文件，添加看门狗相关文件到项目配置
- 更新FWDGT API调用方式，使用新的配置函数
- 增加详细的启动日志输出，便于调试和追踪初始化过程
This commit is contained in:
cbb
2026-05-30 20:03:31 +08:00
parent f63114f5fd
commit 771d34398f
11 changed files with 555 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
GD32E508_DCU_APP/RTE/Device/GD32E508VE/system_gd32e50x.c
+44 -1
View File
@@ -1,4 +1,4 @@
/*!
/*!
\file system_gd32e50x.c
\brief CMSIS Cortex-M33 Device Peripheral Access Layer Source File for
GD32E50x Device Series
@@ -162,6 +162,33 @@ static void _soft_delay_(uint32_t time)
*/
void SystemInit (void)
{
/* ===== DIAG: raw USART0 output at IRC8M (8MHz) ===== */
/* Enable AFIO + GPIOA + USART0 clocks via raw register */
*((volatile uint32_t *)0x40021018U) |= (1U << 14) | (1U << 2) | (1U << 0);
/* PA9 = AF_PP, 50MHz (CTL=0b11, MD=0b11) -> CTL1 bit[4..7]=0b1011 */
{
volatile uint32_t ctl = *((volatile uint32_t *)0x40010804U);
ctl &= ~(0xFU << 4);
ctl |= (0xBU << 4); /* AF_PP 50MHz */
*((volatile uint32_t *)0x40010804U) = ctl;
}
/* USART0 baud: BAUD = 8000000/115200 = 69 */
*((volatile uint32_t *)0x40013808U) = 69U;
/* USART0 CTL0: TE + EN = bit3 + bit13 */
*((volatile uint32_t *)0x40013800U) = (1U << 3) | (1U << 13);
/* Send "APP" via USART0 DATA register */
*((volatile uint32_t *)0x40013804U) = 'A';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = 'P';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = 'P';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = '\r';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = '\n';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
/* ===== END DIAG ===== */
/* FPU settings */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
@@ -196,6 +223,22 @@ void SystemInit (void)
/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
system_clock_config();
/* ===== DIAG: after PLL config, at 180MHz, send "CLK" ===== */
/* Re-enable USART0 at 180MHz: BAUD = 180000000/115200 = 1562.5 = 1563 */
*((volatile uint32_t *)0x40013808U) = 1563U;
*((volatile uint32_t *)0x40013800U) = (1U << 3) | (1U << 13);
*((volatile uint32_t *)0x40013804U) = 'C';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = 'L';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = 'K';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = '\r';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
*((volatile uint32_t *)0x40013804U) = '\n';
while ((*((volatile uint32_t *)0x40013800U) & (1U << 7)) == 0U) {}
/* ===== END DIAG ===== */
#ifdef VECT_TAB_SRAM
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);