cbb
d0b6d9537e
- 在startup_gd32e50x_cl.s中添加USART0早期诊断代码，在Reset_Handler中 发送'R'字符以确认启动过程 - 修改system_gd32e50x.c中的时钟初始化逻辑，支持动态检测当前时钟源 （PLL或IRC8M）并相应调整串口波特率设置 - 在系统时钟配置函数中添加HXTAL故障诊断输出，当外部晶振启动失败时 通过USART0输出"HXTAL FAIL"错误信息 - 在AppSpiCommand类中实现DMA传输机制，使用DMA0_CH2进行SPI0数据发送， 提升传输效率并与BOOT端保持一致 - 重构SPI命令处理逻辑，优化PING命令响应格式，包含APP和BOOT版本信息 以及运行时间统计 - 添加事务过滤机制，忽略全0xFF或全0x00的数据包以及短帧 - 更新配置文件定义APP固件版本号和OTA配置页面地址 - 修复region配置文件中的ROM大小数值精度问题 - 调整NVIC中断优先级设置，优化SPI中断处理
102 lines
2.9 KiB
C
102 lines
2.9 KiB
C
#ifndef REGIONS_GD32E508VE_H
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#define REGIONS_GD32E508VE_H
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//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
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//------ With VS Code: Open Preview for Configuration Wizard -------------------
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// <n> Auto-generated using information from packs
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// <i> Device Family Pack (DFP): GigaDevice::GD32E50x_DFP@1.9.0
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// <h> ROM Configuration
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// =======================
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// <h> __ROM0 (is rx memory: IROM1 from DFP)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region. Default: 0x08000000
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// <i> Contains Startup and Vector Table
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#define __ROM0_BASE 0x08048000
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region. Default: 0x00080000
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#define __ROM0_SIZE 0x00035FFC
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// </h>
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// <h> __ROM1 (unused)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region.
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#define __ROM1_BASE 0x0
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region.
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#define __ROM1_SIZE 0x0
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// </h>
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// <h> __ROM2 (unused)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region.
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#define __ROM2_BASE 0x0
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region.
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#define __ROM2_SIZE 0x0
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// </h>
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// <h> __ROM3 (unused)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region.
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#define __ROM3_BASE 0x0
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region.
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#define __ROM3_SIZE 0x0
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// </h>
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// </h>
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// <h> RAM Configuration
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// =======================
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// <h> __RAM0 (is rwx memory: IRAM1 from DFP)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region. Default: 0x20000000
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// <i> Contains uninitialized RAM, Stack, and Heap
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#define __RAM0_BASE 0x20000000
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region. Default: 0x00020000
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#define __RAM0_SIZE 0x00020000
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// </h>
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// <h> __RAM1 (unused)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region.
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#define __RAM1_BASE 0x0
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region.
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#define __RAM1_SIZE 0x0
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// </h>
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// <h> __RAM2 (unused)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region.
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#define __RAM2_BASE 0x0
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region.
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#define __RAM2_SIZE 0x0
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// </h>
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// <h> __RAM3 (unused)
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// <o> Base address <0x0-0xFFFFFFFF:8>
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// <i> Defines base address of memory region.
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#define __RAM3_BASE 0x0
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// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
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// <i> Defines size of memory region.
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#define __RAM3_SIZE 0x0
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// </h>
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// </h>
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// <h> Stack / Heap Configuration
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// <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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// <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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#define __STACK_SIZE 0x00000200
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#define __HEAP_SIZE 0x00000C00
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// </h>
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#endif /* REGIONS_GD32E508VE_H */
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