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/*!
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\file gd32c10x_misc.c
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\brief MISC driver
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\version 2025-08-07, V1.6.0, firmware for GD32C10x
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32c10x_misc.h"
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/*!
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\brief set the priority group
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\param[in] nvic_prigroup: the NVIC priority group
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\arg NVIC_PRIGROUP_PRE0_SUB4: 0 bits for pre-emption priority, 4 bits for subpriority
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\arg NVIC_PRIGROUP_PRE1_SUB3: 1 bits for pre-emption priority, 3 bits for subpriority
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\arg NVIC_PRIGROUP_PRE2_SUB2: 2 bits for pre-emption priority, 2 bits for subpriority
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\arg NVIC_PRIGROUP_PRE3_SUB1: 3 bits for pre-emption priority, 1 bits for subpriority
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\arg NVIC_PRIGROUP_PRE4_SUB0: 4 bits for pre-emption priority, 0 bits for subpriority
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\param[out] none
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\retval none
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*/
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void nvic_priority_group_set(uint32_t nvic_prigroup)
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{
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/* set the priority group value */
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SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
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}
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/*!
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\brief enable NVIC interrupt request
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\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
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\param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
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\param[in] nvic_irq_sub_priority: the subpriority needed to set
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\param[out] none
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\retval none
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*/
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void nvic_irq_enable(IRQn_Type nvic_irq,
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uint8_t nvic_irq_pre_priority,
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uint8_t nvic_irq_sub_priority)
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{
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uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
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/* use the priority group value to get the temp_pre and the temp_sub */
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switch((SCB->AIRCR) & (uint32_t)0x700U) {
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case NVIC_PRIGROUP_PRE0_SUB4:
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temp_pre = 0U;
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temp_sub = 0x4U;
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break;
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case NVIC_PRIGROUP_PRE1_SUB3:
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temp_pre = 1U;
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temp_sub = 0x3U;
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break;
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case NVIC_PRIGROUP_PRE2_SUB2:
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temp_pre = 2U;
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temp_sub = 0x2U;
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break;
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case NVIC_PRIGROUP_PRE3_SUB1:
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temp_pre = 3U;
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temp_sub = 0x1U;
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break;
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case NVIC_PRIGROUP_PRE4_SUB0:
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temp_pre = 4U;
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temp_sub = 0x0U;
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break;
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default:
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nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
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temp_pre = 2U;
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temp_sub = 0x2U;
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break;
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}
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/* get the temp_priority to fill the NVIC->IP register */
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temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
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temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub));
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temp_priority = temp_priority << 0x04U;
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NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
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/* enable the selected IRQ */
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NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
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}
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/*!
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\brief disable NVIC interrupt request
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\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
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\param[out] none
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\retval none
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*/
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void nvic_irq_disable(IRQn_Type nvic_irq)
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{
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/* disable the selected IRQ.*/
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NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
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}
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/*!
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\brief set the NVIC vector table base address
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\param[in] nvic_vict_tab: the RAM or FLASH base address
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\arg NVIC_VECTTAB_RAM: RAM base address
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\are NVIC_VECTTAB_FLASH: Flash base address
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\param[in] offset: vector table offset
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\param[out] none
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\retval none
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*/
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void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
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{
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SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
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__DSB();
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}
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/*!
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\brief set the state of the low power mode
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\param[in] lowpower_mode: the low power mode state
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\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
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mode by exiting from ISR
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\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
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\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the low power mode can be woke up
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by all the enable and disable interrupts
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\param[out] none
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\retval none
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*/
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void system_lowpower_set(uint8_t lowpower_mode)
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{
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SCB->SCR |= (uint32_t)lowpower_mode;
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}
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/*!
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\brief reset the state of the low power mode
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\param[in] lowpower_mode: the low power mode state
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\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
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mode by exiting from ISR
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\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
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\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the low power mode only can be
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woke up by the enable interrupts
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\param[out] none
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\retval none
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*/
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void system_lowpower_reset(uint8_t lowpower_mode)
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{
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SCB->SCR &= (~(uint32_t)lowpower_mode);
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}
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/*!
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\brief set the systick clock source
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\param[in] systick_clksource: the systick clock source needed to choose
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\arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
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\arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
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\param[out] none
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\retval none
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*/
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void systick_clksource_set(uint32_t systick_clksource)
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{
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if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) {
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/* set the systick clock source from HCLK */
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SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
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} else {
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/* set the systick clock source from HCLK/8 */
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SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
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}
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}
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