110 lines
2.7 KiB
Plaintext
110 lines
2.7 KiB
Plaintext
/*
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* Copyright (c) 2023 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* ----------------------------------------------------------------------------
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Stack seal size definition
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*----------------------------------------------------------------------------*/
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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#define __STACKSEAL_SIZE 8
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#else
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#define __STACKSEAL_SIZE 0
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#endif
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/*----------------------------------------------------------------------------
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Scatter File Definitions definition
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*----------------------------------------------------------------------------*/
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LR_ROM0 __ROM0_BASE __ROM0_SIZE {
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ER_ROM0 __ROM0_BASE __ROM0_SIZE {
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*.o (RESET, +First)
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*(InRoot$$Sections)
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*(+RO +XO)
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}
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) {
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*(Veneer$$CMSE)
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}
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#endif
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RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) {
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*.o(.bss.noinit)
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*.o(.bss.noinit.*)
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}
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RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) {
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*(+RW +ZI)
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}
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#if __HEAP_SIZE > 0
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ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap
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}
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#endif
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ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack
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}
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#if __STACKSEAL_SIZE > 0
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STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack
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}
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#endif
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#if __RAM1_SIZE > 0
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RW_RAM1 __RAM1_BASE __RAM1_SIZE {
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.ANY (+RW +ZI)
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}
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#endif
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#if __RAM2_SIZE > 0
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RW_RAM2 __RAM2_BASE __RAM2_SIZE {
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.ANY (+RW +ZI)
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}
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#endif
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#if __RAM3_SIZE > 0
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RW_RAM3 __RAM3_BASE __RAM3_SIZE {
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.ANY (+RW +ZI)
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}
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#endif
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}
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#if __ROM1_SIZE > 0
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LR_ROM1 __ROM1_BASE __ROM1_SIZE {
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ER_ROM1 +0 __ROM1_SIZE {
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.ANY (+RO +XO)
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}
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}
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#endif
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#if __ROM2_SIZE > 0
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LR_ROM2 __ROM2_BASE __ROM2_SIZE {
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ER_ROM2 +0 __ROM2_SIZE {
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.ANY (+RO +XO)
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}
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}
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#endif
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#if __ROM3_SIZE > 0
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LR_ROM3 __ROM3_BASE __ROM3_SIZE {
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ER_ROM3 +0 __ROM3_SIZE {
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.ANY (+RO +XO)
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}
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}
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#endif
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