2025-09-23 00:27:51 +08:00
|
|
|
#ifndef REGIONS_GD32C103CB_H
|
|
|
|
|
#define REGIONS_GD32C103CB_H
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
|
|
|
|
//------ With VS Code: Open Preview for Configuration Wizard -------------------
|
|
|
|
|
|
|
|
|
|
// <n> Auto-generated using information from packs
|
|
|
|
|
// <i> Device Family Pack (DFP): GigaDevice::GD32C10x_DFP@1.0.1
|
|
|
|
|
|
|
|
|
|
// <h> ROM Configuration
|
|
|
|
|
// =======================
|
|
|
|
|
// <h> __ROM0 (is rx memory: IROM1 from DFP)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region. Default: 0x08000000
|
|
|
|
|
// <i> Contains Startup and Vector Table
|
2026-01-20 01:28:52 +08:00
|
|
|
#define __ROM0_BASE 0x08012000
|
2025-09-23 00:27:51 +08:00
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region. Default: 0x00020000
|
2026-01-04 22:26:22 +08:00
|
|
|
#define __ROM0_SIZE 0x0000C000
|
2025-09-23 00:27:51 +08:00
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> __ROM1 (unused)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region.
|
|
|
|
|
#define __ROM1_BASE 0x0
|
|
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region.
|
|
|
|
|
#define __ROM1_SIZE 0x0
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> __ROM2 (unused)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region.
|
|
|
|
|
#define __ROM2_BASE 0x0
|
|
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region.
|
|
|
|
|
#define __ROM2_SIZE 0x0
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> __ROM3 (unused)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region.
|
|
|
|
|
#define __ROM3_BASE 0x0
|
|
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region.
|
|
|
|
|
#define __ROM3_SIZE 0x0
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> RAM Configuration
|
|
|
|
|
// =======================
|
|
|
|
|
// <h> __RAM0 (is rwx memory: IRAM1 from DFP)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region. Default: 0x20000000
|
|
|
|
|
// <i> Contains uninitialized RAM, Stack, and Heap
|
|
|
|
|
#define __RAM0_BASE 0x20000000
|
|
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region. Default: 0x00008000
|
|
|
|
|
#define __RAM0_SIZE 0x00008000
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> __RAM1 (unused)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region.
|
|
|
|
|
#define __RAM1_BASE 0x0
|
|
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region.
|
|
|
|
|
#define __RAM1_SIZE 0x0
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> __RAM2 (unused)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region.
|
|
|
|
|
#define __RAM2_BASE 0x0
|
|
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region.
|
|
|
|
|
#define __RAM2_SIZE 0x0
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> __RAM3 (unused)
|
|
|
|
|
// <o> Base address <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines base address of memory region.
|
|
|
|
|
#define __RAM3_BASE 0x0
|
|
|
|
|
// <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <i> Defines size of memory region.
|
|
|
|
|
#define __RAM3_SIZE 0x0
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
// <h> Stack / Heap Configuration
|
|
|
|
|
// <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
|
|
|
// <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
|
|
|
#define __STACK_SIZE 0x00000200
|
|
|
|
|
#define __HEAP_SIZE 0x00000C00
|
|
|
|
|
// </h>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#endif /* REGIONS_GD32C103CB_H */
|
