cbb
4c4e47e9e3
添加了完整的Doxygen文档注释到FOC算法模块的所有函数、类和变量，提升了代码可读性和维护性。同时优化了SVPWM算法实现，将atan2f替换为符号法扇区判断，显著提升计算效率（约15周期vs atan2f 300周期），并改进了arm_sin_cos_f32替代sqrtf提高性能。 feat(FOC): 统一电气角度计算避免重复运算 重构代码以统一电气角度计算，在各个控制循环中只计算一次电气角度并传递给需要的函数，避免了多次重复的fmodf运算和角度归一化操作，提升了实时控制性能。 refactor(Filter): 改进α-β观测器角度处理精度 修改角度卡尔曼滤波器在归一化角度空间[0,360)内工作，避免大累积角度的浮点精度损失问题，确保静止状态下不会产生虚假速度，同时保持与下游代码的兼容性。 refactor: 为算法模块添加完整文档注释 为所有算法模块(FOC、Filter、pid、thermal)添加了详细的Doxygen文档注释，包括函数说明、参数描述、返回值说明等，便于代码理解和API文档生成。
1003 lines
30 KiB
C
1003 lines
30 KiB
C
/*!
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\file system_gd32c10x.c
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\brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for
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GD32C10x Device Series
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*/
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/* Copyright (c) 2009 - 2014 ARM LIMITED
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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#include "gd32c10x.h"
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/* system frequency define */
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#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
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#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
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#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
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/* Vector Table base offset */
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/** @brief APP_BASE 宏定义 */
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#define APP_BASE ((uint32_t)0x08012000U) /*!< main FLASH base address */
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#define VECT_TAB_OFFSET (uint32_t)APP_BASE-FLASH_BASE /* This value must be a multiple of 0x200. */
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/* select a system clock by uncommenting the following line */
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/* use IRC8M */
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// #define __SYSTEM_CLOCK_IRC8M (uint32_t)(__IRC8M)
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// #define __SYSTEM_CLOCK_48M_PLL_IRC8M (uint32_t)(48000000)
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//#define __SYSTEM_CLOCK_72M_PLL_IRC8M (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_108M_PLL_IRC8M (uint32_t)(108000000)
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// #define __SYSTEM_CLOCK_120M_PLL_IRC8M (uint32_t)(120000000)
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/* use HXTAL(CK_HXTAL = 8M) */
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// #define __SYSTEM_CLOCK_HXTAL (uint32_t)(__HXTAL)
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// #define __SYSTEM_CLOCK_48M_PLL_HXTAL (uint32_t)(48000000)
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//#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
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//#define __SYSTEM_CLOCK_108M_PLL_HXTAL (uint32_t)(108000000)
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#define __SYSTEM_CLOCK_120M_PLL_HXTAL (uint32_t)(120000000)
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/* The following is to prevent Vcore fluctuations caused by frequency switching.
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It is strongly recommended to include it to avoid issues caused by self-removal. */
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/** @brief RCU_MODIFY_4 宏定义 */
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#define RCU_MODIFY_4(__delay) do{ \
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volatile uint32_t i, reg; \
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if(0 != __delay){ \
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/* Insert a software delay */ \
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for(i=0; i<__delay; i++){ \
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} \
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reg = RCU_CFG0; \
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reg &= ~(RCU_CFG0_AHBPSC); \
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reg |= RCU_AHB_CKSYS_DIV2; \
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/* AHB = SYSCLK/2 */ \
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RCU_CFG0 = reg; \
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/* Insert a software delay */ \
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for(i=0; i<__delay; i++){ \
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} \
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reg = RCU_CFG0; \
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reg &= ~(RCU_CFG0_AHBPSC); \
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reg |= RCU_AHB_CKSYS_DIV4; \
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/* AHB = SYSCLK/4 */ \
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RCU_CFG0 = reg; \
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/* Insert a software delay */ \
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for(i=0; i<__delay; i++){ \
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} \
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reg = RCU_CFG0; \
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reg &= ~(RCU_CFG0_AHBPSC); \
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reg |= RCU_AHB_CKSYS_DIV8; \
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/* AHB = SYSCLK/8 */ \
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RCU_CFG0 = reg; \
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/* Insert a software delay */ \
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for(i=0; i<__delay; i++){ \
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} \
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reg = RCU_CFG0; \
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reg &= ~(RCU_CFG0_AHBPSC); \
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reg |= RCU_AHB_CKSYS_DIV16; \
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/* AHB = SYSCLK/16 */ \
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RCU_CFG0 = reg; \
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/* Insert a software delay */ \
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for(i=0; i<__delay; i++){ \
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} \
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} \
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}while(0)
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/** @brief SEL_IRC8M 宏定义 */
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#define SEL_IRC8M 0x00U
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/** @brief SEL_HXTAL 宏定义 */
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#define SEL_HXTAL 0x01U
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/** @brief SEL_PLL 宏定义 */
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#define SEL_PLL 0x02U
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/* set the system clock frequency and declare the system clock configuration function */
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#ifdef __SYSTEM_CLOCK_IRC8M
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_IRC8M;
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/**
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* @brief system_clock_8m_irc8m 函数
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* @return void
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*/
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static void system_clock_8m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_IRC8M;
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/**
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* @brief system_clock_48m_irc8m 函数
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* @return void
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*/
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static void system_clock_48m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M;
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/**
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* @brief system_clock_72m_irc8m 函数
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* @return void
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*/
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static void system_clock_72m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_IRC8M;
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/**
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* @brief system_clock_108m_irc8m 函数
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* @return void
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*/
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static void system_clock_108m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_IRC8M;
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/**
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* @brief system_clock_120m_irc8m 函数
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* @return void
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*/
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static void system_clock_120m_irc8m(void);
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#elif defined (__SYSTEM_CLOCK_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_HXTAL;
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/**
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* @brief system_clock_hxtal 函数
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* @return void
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*/
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static void system_clock_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_48M_PLL_HXTAL;
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/**
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* @brief system_clock_48m_hxtal 函数
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* @return void
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*/
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static void system_clock_48m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
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/**
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* @brief system_clock_72m_hxtal 函数
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* @return void
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*/
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static void system_clock_72m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_108M_PLL_HXTAL;
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/**
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* @brief system_clock_108m_hxtal 函数
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* @return void
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*/
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static void system_clock_108m_hxtal(void);
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#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
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uint32_t SystemCoreClock = __SYSTEM_CLOCK_120M_PLL_HXTAL;
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/**
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* @brief system_clock_120m_hxtal 函数
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* @return void
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*/
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static void system_clock_120m_hxtal(void);
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#endif /* __SYSTEM_CLOCK_IRC8M */
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/* configure the system clock */
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/**
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* @brief system_clock_config 函数
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* @return void
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*/
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static void system_clock_config(void);
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/* software delay to prevent the impact of Vcore fluctuations.
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It is strongly recommended to include it to avoid issues caused by self-removal. */
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/**
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* @brief _soft_delay_ 函数
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* @param[in] time 参数
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* @return void
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*/
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static void _soft_delay_(uint32_t time)
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{
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__IO uint32_t i;
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for(i=0; i<time*10; i++){
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}
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}
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/*!
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\brief setup the micro controller system, initialize the system
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\param[in] none
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\param[out] none
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\retval none
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*/
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void SystemInit (void)
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{
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/* FPU settings */
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* reset the RCU clock configuration to the default reset state */
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/* Set IRC8MEN bit */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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while(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) {
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}
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if(((RCU_CFG0 & RCU_CFG0_SCSS) == RCU_SCSS_PLL)){
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RCU_MODIFY_4(0x50);
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}
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RCU_CFG0 &= ~RCU_CFG0_SCS;
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_soft_delay_(200);
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/* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
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RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
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/* disable all interrupts */
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RCU_INT = 0x00ff0000U;
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/* Reset CFG0 and CFG1 registers */
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RCU_CFG0 = 0x00000000U;
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RCU_CFG1 = 0x00000000U;
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/* reset HXTALBPS bit */
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RCU_CTL &= ~(RCU_CTL_HXTALBPS);
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/* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
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system_clock_config();
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#ifdef VECT_TAB_SRAM
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nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
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#else
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nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
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#endif
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}
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/*!
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\brief configure the system clock
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_config(void)
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{
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#ifdef __SYSTEM_CLOCK_IRC8M
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system_clock_8m_irc8m();
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#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
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system_clock_48m_irc8m();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
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system_clock_72m_irc8m();
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#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
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system_clock_108m_irc8m();
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#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
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system_clock_120m_irc8m();
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#elif defined (__SYSTEM_CLOCK_HXTAL)
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system_clock_hxtal();
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#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
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system_clock_48m_hxtal();
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#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
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system_clock_72m_hxtal();
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#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
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system_clock_108m_hxtal();
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#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
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system_clock_120m_hxtal();
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#endif /* __SYSTEM_CLOCK_IRC8M */
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}
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#ifdef __SYSTEM_CLOCK_IRC8M
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/*!
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\brief configure the system clock to 8M by IRC8M
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_8m_irc8m(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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__IO uint32_t reg_temp;
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/* enable IRC8M */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
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}
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while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
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/* if fail */
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if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
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while(1){
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}
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}
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
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/* APB2 = AHB/1 */
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RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
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/* APB1 = AHB/2 */
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RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
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reg_temp = RCU_CFG0;
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/* select IRC8M as system clock */
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reg_temp &= ~RCU_CFG0_SCS;
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reg_temp |= RCU_CKSYSSRC_IRC8M;
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RCU_CFG0 = reg_temp;
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/* wait until IRC8M is selected as system clock */
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while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
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}
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}
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#elif defined (__SYSTEM_CLOCK_48M_PLL_IRC8M)
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/*!
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\brief configure the system clock to 48M by PLL which selects IRC8M as its clock source
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\param[in] none
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\param[out] none
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\retval none
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*/
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static void system_clock_48m_irc8m(void)
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{
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uint32_t timeout = 0U;
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uint32_t stab_flag = 0U;
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__IO uint32_t reg_temp;
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|
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/* enable IRC8M */
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RCU_CTL |= RCU_CTL_IRC8MEN;
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|
|
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/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
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do{
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timeout++;
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stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
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}
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while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
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if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
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while(1){
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|
}
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}
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FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_1;
|
|
|
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/* IRC8M is stable */
|
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/* AHB = SYSCLK */
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RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_IRC8M/2) * 12 = 48 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= RCU_PLL_MUL12;
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M)
|
|
/*!
|
|
\brief configure the system clock to 72M by PLL which selects IRC8M as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_72m_irc8m(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable IRC8M */
|
|
RCU_CTL |= RCU_CTL_IRC8MEN;
|
|
|
|
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
|
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_2;
|
|
|
|
/* IRC8M is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_IRC8M/2) * 18 = 72 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= RCU_PLL_MUL18;
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_108M_PLL_IRC8M)
|
|
/*!
|
|
\brief configure the system clock to 108M by PLL which selects IRC8M as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_108m_irc8m(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable IRC8M */
|
|
RCU_CTL |= RCU_CTL_IRC8MEN;
|
|
|
|
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
|
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3;
|
|
|
|
/* IRC8M is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_IRC8M/2) * 27 = 108 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= RCU_PLL_MUL27;
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_120M_PLL_IRC8M)
|
|
/*!
|
|
\brief configure the system clock to 120M by PLL which selects IRC8M as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_120m_irc8m(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable IRC8M */
|
|
RCU_CTL |= RCU_CTL_IRC8MEN;
|
|
|
|
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
|
|
}while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3;
|
|
|
|
/* IRC8M is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_IRC8M/2) * 30 = 120 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= RCU_PLL_MUL30;
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to HXTAL
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select HXTAL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_HXTAL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until HXTAL is selected as system clock */
|
|
while(0 == (RCU_CFG0 & RCU_SCSS_HXTAL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_48M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 48M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_48m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_1;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_PREDIV0) * 12 = 48 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL12);
|
|
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */
|
|
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
|
}
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 72M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_72m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_2;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_PREDIV0) * 18 = 72 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL18);
|
|
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */
|
|
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
|
}
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_108M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 108M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_108m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL27);
|
|
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */
|
|
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0){
|
|
}
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
|
|
#elif defined (__SYSTEM_CLOCK_120M_PLL_HXTAL)
|
|
/*!
|
|
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
static void system_clock_120m_hxtal(void)
|
|
{
|
|
uint32_t timeout = 0U;
|
|
uint32_t stab_flag = 0U;
|
|
__IO uint32_t reg_temp;
|
|
|
|
/* enable HXTAL */
|
|
RCU_CTL |= RCU_CTL_HXTALEN;
|
|
|
|
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
|
do{
|
|
timeout++;
|
|
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
|
|
}while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
|
|
|
/* if fail */
|
|
if(0U == (RCU_CTL & RCU_CTL_HXTALSTB)){
|
|
while(1){
|
|
}
|
|
}
|
|
|
|
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | FMC_WAIT_STATE_3;
|
|
|
|
/* HXTAL is stable */
|
|
/* AHB = SYSCLK */
|
|
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
|
/* APB2 = AHB/1 */
|
|
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
|
/* APB1 = AHB/2 */
|
|
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
|
|
|
|
/* CK_PLL = (CK_PREDIV0) * 30 = 120 MHz */
|
|
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
|
|
RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL30);
|
|
|
|
RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
|
|
|
|
/* CK_PREDIV0 = (CK_HXTAL)/2 *10 /10 = 4 MHz */
|
|
RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL10 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV10);
|
|
|
|
/* enable PLL1 */
|
|
RCU_CTL |= RCU_CTL_PLL1EN;
|
|
/* wait till PLL1 is ready */
|
|
while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
|
|
}
|
|
|
|
/* enable PLL */
|
|
RCU_CTL |= RCU_CTL_PLLEN;
|
|
|
|
/* wait until PLL is stable */
|
|
while(0U == (RCU_CTL & RCU_CTL_PLLSTB)){
|
|
}
|
|
|
|
reg_temp = RCU_CFG0;
|
|
/* select PLL as system clock */
|
|
reg_temp &= ~RCU_CFG0_SCS;
|
|
reg_temp |= RCU_CKSYSSRC_PLL;
|
|
RCU_CFG0 = reg_temp;
|
|
|
|
/* wait until PLL is selected as system clock */
|
|
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
|
|
}
|
|
}
|
|
#endif /* __SYSTEM_CLOCK_IRC8M */
|
|
|
|
/*!
|
|
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void SystemCoreClockUpdate (void)
|
|
{
|
|
uint32_t sws = 0U;
|
|
uint32_t pllsel = 0U, pllpresel = 0U, predv0sel = 0U, pllmf,ck_src = 0U;
|
|
uint32_t predv0 = 0U, predv1 = 0U, pll1mf = 0U,idx = 0U,clk_exp = 0U;
|
|
/* exponent of AHB clock divider */
|
|
const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
|
|
|
sws = GET_BITS(RCU_CFG0, 2, 3);
|
|
switch(sws){
|
|
/* IRC8M is selected as CK_SYS */
|
|
case SEL_IRC8M:
|
|
SystemCoreClock = IRC8M_VALUE;
|
|
break;
|
|
/* HXTAL is selected as CK_SYS */
|
|
case SEL_HXTAL:
|
|
SystemCoreClock = HXTAL_VALUE;
|
|
break;
|
|
/* PLL is selected as CK_SYS */
|
|
case SEL_PLL:
|
|
/* PLL clock source selection, HXTAL, IRC48M or IRC8M/2 */
|
|
pllsel = (RCU_CFG0 & RCU_CFG0_PLLSEL);
|
|
|
|
if(RCU_PLLSRC_HXTAL_IRC48M == pllsel){
|
|
/* PLL clock source is HXTAL or IRC48M */
|
|
pllpresel = (RCU_CFG1 & RCU_CFG1_PLLPRESEL);
|
|
|
|
if(RCU_PLLPRESRC_HXTAL == pllpresel){
|
|
/* PLL clock source is HXTAL */
|
|
ck_src = HXTAL_VALUE;
|
|
}else{
|
|
/* PLL clock source is IRC48 */
|
|
ck_src = IRC48M_VALUE;
|
|
}
|
|
|
|
predv0sel = (RCU_CFG1 & RCU_CFG1_PREDV0SEL);
|
|
/* source clock use PLL1 */
|
|
if(RCU_PREDV0SRC_CKPLL1 == predv0sel){
|
|
predv1 = ((RCU_CFG1 & RCU_CFG1_PREDV1) >> 4) + 1U;
|
|
pll1mf = ((RCU_CFG1 & RCU_CFG1_PLL1MF) >> 8) + 2U;
|
|
if(17U == pll1mf){
|
|
pll1mf = 20U;
|
|
}
|
|
ck_src = (ck_src/predv1)*pll1mf;
|
|
}
|
|
predv0 = (RCU_CFG1 & RCU_CFG1_PREDV0) + 1U;
|
|
ck_src /= predv0;
|
|
}else{
|
|
/* PLL clock source is IRC8M/2 */
|
|
ck_src = IRC8M_VALUE/2U;
|
|
}
|
|
|
|
/* PLL multiplication factor */
|
|
pllmf = GET_BITS(RCU_CFG0, 18, 21);
|
|
if((RCU_CFG0 & RCU_CFG0_PLLMF_4)){
|
|
pllmf |= 0x10U;
|
|
}
|
|
if(pllmf < 15U){
|
|
pllmf += 2U;
|
|
}else{
|
|
pllmf += 1U;
|
|
}
|
|
SystemCoreClock = ck_src*pllmf;
|
|
if(15U == pllmf){
|
|
SystemCoreClock = ck_src*6U + ck_src/2U;
|
|
}
|
|
|
|
break;
|
|
/* IRC8M is selected as CK_SYS */
|
|
default:
|
|
SystemCoreClock = IRC8M_VALUE;
|
|
break;
|
|
}
|
|
/* calculate AHB clock frequency */
|
|
idx = GET_BITS(RCU_CFG0, 4, 7);
|
|
clk_exp = ahb_exp[idx];
|
|
SystemCoreClock >>= clk_exp;
|
|
}
|
|
|
|
#ifdef __FIRMWARE_VERSION_DEFINE
|
|
/*!
|
|
\brief get firmware version
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval firmware version
|
|
*/
|
|
uint32_t gd32c10x_firmware_version_get(void)
|
|
{
|
|
return __GD32C10X_STDPERIPH_VERSION;
|
|
}
|
|
#endif /* __FIRMWARE_VERSION_DEFINE */
|