feat(canfd): 切换 CANFD 接收为中断驱动和环形缓冲机制

- 将 CANFD 接收机制由轮询改为 FIFO0 的中断事件驱动处理
- 实现循环取空硬件 FIFO0，提高接收效率和响应速度
- 引入环形缓冲区缓存接收帧，支持多路通道多帧队列管理
- 置位解析任务标志位，实现接收数据的异步解析
- 增加接收中断统计，包括 FIFO 满和溢出计数
- 重构临界区代码，使用自定义函数保护中断状态
- 修改接收过滤器配置，支持按掩码匹配标准帧进入 FIFO0
- 使能 CAN FIFO0 多种中断标志，包括非空、满和溢出中断

GD32E508_DCU_APP/RTE/Device/GD32E508VE/regions_GD32E508VE.h

@@ -14,10 +14,10 @@
 //   <o> Base address <0x0-0xFFFFFFFF:8>
 //   <i> Defines base address of memory region. Default: 0x08000000
 //   <i> Contains Startup and Vector Table
-#define __ROM0_BASE 0x08000000
+#define __ROM0_BASE 0x08048000
 //   <o> Region size [bytes] <0x0-0xFFFFFFFF:8>
 //   <i> Defines size of memory region. Default: 0x00080000
-#define __ROM0_SIZE 0x00080000
+#define __ROM0_SIZE 0x00036000
 // </h>
 
 // <h> __ROM1 (unused)

GD32E508_DCU_APP/RTE/Device/GD32E508VE/system_gd32e50x.c

@@ -31,7 +31,7 @@
 #define __IRC8M           (IRC8M_VALUE)            /* internal 8 MHz RC oscillator frequency */
 #define __HXTAL           (HXTAL_VALUE)            /* high speed crystal oscillator frequency */
 
-#define VECT_TAB_OFFSET  (uint32_t)0x00            /* vector table base offset */
+#define VECT_TAB_OFFSET  (uint32_t)0x00048000      /* vector table base offset */
 
 /* select a system clock by uncommenting the following line */
 /* use IRC8M */
@@ -142,8 +142,12 @@ static void system_clock_180m_hxtal(void);
 
 /* configure the system clock */
 static void system_clock_config(void);
-/* software delay to prevent the impact of Vcore fluctuations.
-   It is strongly recommended to include it to avoid issues caused by self-removal. */
+/*!
+    \brief      software delay to prevent the impact of Vcore fluctuations
+    \param[in]  time delay factor
+    \param[out] none
+    \retval     none
+*/
 static void _soft_delay_(uint32_t time)
 {
     __IO uint32_t i;
@@ -997,7 +1001,23 @@ static void system_clock_180m_hxtal(void)
     RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
     RCU_CFG0 |= RCU_PLL_MUL45;
 
-#elif (defined(GD32E50X_CL) || defined(GD32E508))
+#elif defined(GD32E508)
+    /* GD32E508 + 8MHz HXTAL:
+       CK_PREDIV0 = (CK_HXTAL)/2 *8 /8 = 4 MHz
+       CK_PLL     = CK_PREDIV0 * 45      = 180 MHz */
+    RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
+    RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL45);
+
+    RCU_CFG1 &= ~(RCU_CFG1_PLLPRESEL | RCU_CFG1_PREDV0SEL | RCU_CFG1_PLL1MF | RCU_CFG1_PREDV1 | RCU_CFG1_PREDV0);
+    RCU_CFG1 |= (RCU_PLLPRESRC_HXTAL | RCU_PREDV0SRC_CKPLL1 | RCU_PLL1_MUL8 | RCU_PREDV1_DIV2 | RCU_PREDV0_DIV8);
+
+    /* enable PLL1 */
+    RCU_CTL |= RCU_CTL_PLL1EN;
+    /* wait till PLL1 is ready */
+    while((RCU_CTL & RCU_CTL_PLL1STB) == 0U){
+    }
+
+#elif defined(GD32E50X_CL)
     /* CK_PLL = (CK_PREDIV0) * 45 = 180 MHz */ 
     RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4 | RCU_CFG0_PLLMF_5);
     RCU_CFG0 |= (RCU_PLLSRC_HXTAL_IRC48M | RCU_PLL_MUL45);