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523 lines
16 KiB
Plaintext
523 lines
16 KiB
Plaintext
/*!
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\file gd32e50x_pmu.c
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\brief PMU driver
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\version 2026-02-09, V1.7.0, firmware for GD32E50x
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32e50x_pmu.h"
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/*!
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\brief reset PMU registers
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_deinit(void)
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{
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/* reset PMU */
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rcu_periph_reset_enable(RCU_PMURST);
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rcu_periph_reset_disable(RCU_PMURST);
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}
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/*!
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\brief select low voltage detector threshold
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\param[in] lvdt_n:
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only one parameter can be selected which is shown as below:
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\arg PMU_LVDT_0: voltage threshold is 2.1V
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\arg PMU_LVDT_1: voltage threshold is 2.3V
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\arg PMU_LVDT_2: voltage threshold is 2.4V
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\arg PMU_LVDT_3: voltage threshold is 2.6V
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\arg PMU_LVDT_4: voltage threshold is 2.7V
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\arg PMU_LVDT_5: voltage threshold is 2.9V
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\arg PMU_LVDT_6: voltage threshold is 3.0V
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\arg PMU_LVDT_7: voltage threshold is 3.1V
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\param[out] none
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\retval none
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*/
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void pmu_lvd_select(uint32_t lvdt_n)
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{
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/* disable LVD */
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PMU_CTL0 &= ~PMU_CTL0_LVDEN;
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/* clear LVDT bits */
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PMU_CTL0 &= ~PMU_CTL0_LVDT;
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/* set LVDT bits according to lvdt_n */
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PMU_CTL0 |= lvdt_n;
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/* enable LVD */
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PMU_CTL0 |= PMU_CTL0_LVDEN;
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}
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/*!
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\brief disable PMU LVD
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_lvd_disable(void)
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{
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/* disable LVD */
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PMU_CTL0 &= ~PMU_CTL0_LVDEN;
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}
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/*!
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\brief enable high-driver mode
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this bit set by software only when IRC8M or HXTAL used as system clock
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_highdriver_mode_enable(void)
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{
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PMU_CTL0 |= PMU_CTL0_HDEN;
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}
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/*!
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\brief disable high-driver mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_highdriver_mode_disable(void)
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{
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PMU_CTL0 &= ~PMU_CTL0_HDEN;
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}
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/*!
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\brief switch high-driver mode
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this bit set by software only when IRC8M or HXTAL used as system clock
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\param[in] highdr_switch:
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only one parameter can be selected which is shown as below:
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\arg PMU_HIGHDR_SWITCH_NONE: disable high-driver mode switch
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\arg PMU_HIGHDR_SWITCH_EN: enable high-driver mode switch
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\param[out] none
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\retval none
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*/
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void pmu_highdriver_switch_select(uint32_t highdr_switch)
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{
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/* wait for HDRF flag set */
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while(SET != pmu_flag_get(PMU_FLAG_HDRF)){
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}
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PMU_CTL0 &= ~PMU_CTL0_HDS;
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PMU_CTL0 |= highdr_switch;
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}
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/*!
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\brief enable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_lowdriver_mode_enable(void)
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{
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PMU_CTL0 |= PMU_CTL0_LDEN;
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}
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/*!
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\brief disable low-driver mode in deep-sleep/deep-sleep 1/deep-sleep 2 mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_lowdriver_mode_disable(void)
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{
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PMU_CTL0 &= ~PMU_CTL0_LDEN;
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}
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/*!
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\brief in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use low power LDO
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\param[in] mode:
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only one parameter can be selected which is shown as below:
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\arg PMU_NORMALDR_LOWPWR: normal driver when use low power LDO
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\arg PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and use low power LDO
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\param[out] none
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\retval none
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*/
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void pmu_lowpower_driver_config(uint32_t mode)
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{
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PMU_CTL0 &= ~PMU_CTL0_LDLP;
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PMU_CTL0 |= mode;
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}
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/*!
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\brief in deep-sleep/deep-sleep 1/deep-sleep 2 mode, driver mode when use normal power LDO
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\param[in] mode:
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only one parameter can be selected which is shown as below:
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\arg PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO
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\arg PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and use normal power LDO
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\param[out] none
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\retval none
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*/
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void pmu_normalpower_driver_config(uint32_t mode)
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{
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PMU_CTL0 &= ~PMU_CTL0_LDNP;
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PMU_CTL0 |= mode;
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}
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/*!
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\brief PMU work at sleep mode
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\param[in] sleepmodecmd:
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only one parameter can be selected which is shown as below:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_sleepmode(uint8_t sleepmodecmd)
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{
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/* clear sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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/* select WFI or WFE command to enter sleep mode */
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if(WFI_CMD == sleepmodecmd){
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__WFI();
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}else{
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__SEV();
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__WFE();
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__WFE();
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}
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}
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/*!
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\brief PMU work at deepsleep mode
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\param[in] ldo:
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only one parameter can be selected which is shown as below:
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\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode
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\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
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\param[in] lowdrive:
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only one parameter can be selected which is shown as below:
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\arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep mode
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\arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep mode
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\param[in] deepsleepmodecmd:
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only one parameter can be selected which is shown as below:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd)
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{
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/* clear stbmod and ldolp bits and low drive bits */
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PMU_CTL0 &= ~((uint32_t)(PMU_CTL0_STBMOD | PMU_CTL0_LDOLP | PMU_CTL0_LDEN | PMU_CTL0_LDNP | PMU_CTL0_LDLP));
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/* clear deep-sleep 1/2 mode enable bits */
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PMU_CTL1 &= ~(PMU_CTL1_DPMOD1 | PMU_CTL1_DPMOD2);
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/* set ldolp bit according to pmu_ldo */
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PMU_CTL0 |= ldo;
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/* low drive mode config in deep-sleep mode */
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if(PMU_LOWDRIVER_ENABLE == lowdrive){
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if(PMU_LDO_NORMAL == ldo){
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PMU_CTL0 |= (uint32_t)(PMU_CTL0_LDEN | PMU_CTL0_LDNP);
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}else{
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PMU_CTL0 |= (uint32_t)(PMU_CTL0_LDEN | PMU_CTL0_LDLP);
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}
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}
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/* set sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* select WFI or WFE command to enter deepsleep mode */
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if(WFI_CMD == deepsleepmodecmd){
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__WFI();
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}else{
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__SEV();
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__WFE();
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__WFE();
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}
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/* reset sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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}
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/*!
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\brief PMU work at deepsleep mode 1
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\param[in] ldo:
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only one parameter can be selected which is shown as below:
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\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode 1
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\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode 1
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\param[in] lowdrive:
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only one parameter can be selected which is shown as below:
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\arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep 1 mode
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\arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep 1 mode
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\param[in] deepsleepmode1cmd:
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only one parameter can be selected which is shown as below:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_deepsleepmode_1(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmode1cmd)
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{
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/* clear stbmod and ldolp bits and low drive bits */
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PMU_CTL0 &= ~((uint32_t)(PMU_CTL0_STBMOD | PMU_CTL0_LDOLP | PMU_CTL0_LDEN | PMU_CTL0_LDNP | PMU_CTL0_LDLP));
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/* clear deep-sleep 2 mode enable bit */
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PMU_CTL1 &= ~PMU_CTL1_DPMOD2;
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/* enable deep-sleep 1 mode */
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PMU_CTL1 |= PMU_CTL1_DPMOD1;
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/* set ldolp bit according to pmu_ldo */
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PMU_CTL0 |= ldo;
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/* low drive mode config in deep-sleep 1 mode */
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if(PMU_LOWDRIVER_ENABLE == lowdrive){
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if(PMU_LDO_NORMAL == ldo){
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PMU_CTL0 |= (uint32_t)(PMU_CTL0_LDEN | PMU_CTL0_LDNP);
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}else{
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PMU_CTL0 |= (uint32_t)(PMU_CTL0_LDEN | PMU_CTL0_LDLP);
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}
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}
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/* set sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* select WFI or WFE command to enter deepsleep mode 1 */
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if(WFI_CMD == deepsleepmode1cmd){
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__WFI();
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}else{
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__SEV();
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__WFE();
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__WFE();
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}
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/* reset sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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PMU_CTL1 &= ~PMU_CTL1_DPMOD1;
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}
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/*!
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\brief PMU work at deepsleep mode 2
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\param[in] ldo:
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only one parameter can be selected which is shown as below:
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\arg PMU_LDO_NORMAL: LDO normal work when pmu enter deepsleep mode 2
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\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode 2
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\param[in] lowdrive:
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only one parameter can be selected which is shown as below:
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\arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep 2 mode
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\arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep 2 mode
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\param[in] deepsleepmode2cmd:
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only one parameter can be selected which is shown as below:
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\arg WFI_CMD: use WFI command
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\arg WFE_CMD: use WFE command
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\param[out] none
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\retval none
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*/
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void pmu_to_deepsleepmode_2(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmode2cmd)
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{
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/* clear stbmod and ldolp bits and low drive bits */
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PMU_CTL0 &= ~((uint32_t)(PMU_CTL0_STBMOD | PMU_CTL0_LDOLP | PMU_CTL0_LDEN | PMU_CTL0_LDNP | PMU_CTL0_LDLP));
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/* clear deep-sleep 1 mode enable bit */
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PMU_CTL1 &= ~PMU_CTL1_DPMOD1;
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/* enable deep-sleep 2 mode */
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PMU_CTL1 |= PMU_CTL1_DPMOD2;
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/* set ldolp bit according to pmu_ldo */
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PMU_CTL0 |= ldo;
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/* low drive mode config in deep-sleep 2 mode */
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if(PMU_LOWDRIVER_ENABLE == lowdrive){
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if(PMU_LDO_NORMAL == ldo){
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PMU_CTL0 |= (uint32_t)(PMU_CTL0_LDEN | PMU_CTL0_LDNP);
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}else{
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PMU_CTL0 |= (uint32_t)(PMU_CTL0_LDEN | PMU_CTL0_LDLP);
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}
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}
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/* set sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* select WFI or WFE command to enter deepsleep mode 2 */
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if(WFI_CMD == deepsleepmode2cmd){
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__WFI();
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}else{
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__SEV();
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__WFE();
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__WFE();
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}
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/* reset sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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PMU_CTL1 &= ~PMU_CTL1_DPMOD2;
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}
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/*!
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\brief pmu work at standby mode
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_to_standbymode(void)
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{
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/* set stbmod bit */
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PMU_CTL0 |= PMU_CTL0_STBMOD;
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/* reset wakeup flag */
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PMU_CTL0 |= PMU_CTL0_WURST;
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/* set sleepdeep bit of Cortex-M33 system control register */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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REG32( 0xE000E010U ) &= 0x00010004U;
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REG32( 0xE000E180U ) = 0XFFFFFFF7U;
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REG32( 0xE000E184U ) = 0XFFFFFDFFU;
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REG32( 0xE000E188U ) = 0xFFFFFFFFU;
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/* select WFI command to enter standby mode */
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__WFI();
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}
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/*!
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\brief enable PMU wakeup pin
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\param[in] wakeup_pin:
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one or more parameters can be selected which are shown as below:
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\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
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\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
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\arg PMU_WAKEUP_PIN2: WKUP Pin 2 (PE6)
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\arg PMU_WAKEUP_PIN3: WKUP Pin 3 (PA2)
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\arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
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\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
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\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
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\arg PMU_WAKEUP_PIN7: WKUP Pin 7 (PF8)
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\param[out] none
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\retval none
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*/
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void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
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{
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PMU_CS0 |= wakeup_pin;
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}
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/*!
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\brief disable PMU wakeup pin
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\param[in] wakeup_pin:
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one or more parameters can be selected which are shown as below:
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\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
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\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
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\arg PMU_WAKEUP_PIN2: WKUP Pin 2 (PE6)
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\arg PMU_WAKEUP_PIN3: WKUP Pin 3 (PA2)
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\arg PMU_WAKEUP_PIN4: WKUP Pin 4 (PC5)
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\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
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\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
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\arg PMU_WAKEUP_PIN7: WKUP Pin 7 (PF8)
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\param[out] none
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\retval none
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*/
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void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
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{
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PMU_CS0 &= ~(wakeup_pin);
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}
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/*!
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\brief enable backup domain write
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\param[in] none
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\param[out] none
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\retval none
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*/
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void pmu_backup_write_enable(void)
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{
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PMU_CTL0 |= PMU_CTL0_BKPWEN;
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}
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/*!
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\brief disable backup domain write
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\param[in] none
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void pmu_backup_write_disable(void)
|
|
{
|
|
PMU_CTL0 &= ~PMU_CTL0_BKPWEN;
|
|
}
|
|
|
|
/*!
|
|
\brief get flag state
|
|
\param[in] flag:
|
|
only one parameter can be selected which is shown as below:
|
|
\arg PMU_FLAG_WAKEUP: wakeup flag
|
|
\arg PMU_FLAG_STANDBY: standby flag
|
|
\arg PMU_FLAG_LVD: lvd flag
|
|
\arg PMU_FLAG_HDRF: high-driver ready flag
|
|
\arg PMU_FLAG_HDSRF: high-driver switch ready flag
|
|
\arg PMU_FLAG_LDRF: low-driver mode ready flag
|
|
\arg PMU_FLAG_DEEPSLEEP_1: deep-sleep 1 mode status flag
|
|
\arg PMU_FLAG_DEEPSLEEP_2: deep-sleep 2 mode status flag
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus pmu_flag_get(uint32_t flag)
|
|
{
|
|
FlagStatus ret = RESET;
|
|
|
|
if(RESET != (flag & BIT(31))){
|
|
flag &= ~BIT(31);
|
|
if(PMU_CS1 & flag){
|
|
ret = SET;
|
|
}
|
|
}else{
|
|
if(PMU_CS0 & flag){
|
|
ret = SET;
|
|
}
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*!
|
|
\brief clear flag bit
|
|
\param[in] flag:
|
|
only one parameter can be selected which is shown as below:
|
|
\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
|
|
\arg PMU_FLAG_RESET_STANDBY: reset standby flag
|
|
\arg PMU_FLAG_RESET_DEEPSLEEP_1: reset deep-sleep 1 mode status flag
|
|
\arg PMU_FLAG_RESET_DEEPSLEEP_2: reset deep-sleep 2 mode status flag
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void pmu_flag_clear(uint32_t flag)
|
|
{
|
|
switch(flag){
|
|
case PMU_FLAG_RESET_WAKEUP:
|
|
/* reset wakeup flag */
|
|
PMU_CTL0 |= PMU_CTL0_WURST;
|
|
break;
|
|
case PMU_FLAG_RESET_STANDBY:
|
|
/* reset standby flag */
|
|
PMU_CTL0 |= PMU_CTL0_STBRST;
|
|
break;
|
|
case PMU_FLAG_RESET_DEEPSLEEP_1:
|
|
/* reset deep-sleep 1 mode status flag */
|
|
PMU_CS1 &= ~PMU_CS1_DPF1;
|
|
break;
|
|
case PMU_FLAG_RESET_DEEPSLEEP_2:
|
|
/* reset deep-sleep 2 mode status flag */
|
|
PMU_CS1 &= ~PMU_CS1_DPF2;
|
|
break;
|
|
default :
|
|
break;
|
|
}
|
|
}
|