cbb
4c4e47e9e3
添加了完整的Doxygen文档注释到FOC算法模块的所有函数、类和变量，提升了代码可读性和维护性。同时优化了SVPWM算法实现，将atan2f替换为符号法扇区判断，显著提升计算效率（约15周期vs atan2f 300周期），并改进了arm_sin_cos_f32替代sqrtf提高性能。 feat(FOC): 统一电气角度计算避免重复运算 重构代码以统一电气角度计算，在各个控制循环中只计算一次电气角度并传递给需要的函数，避免了多次重复的fmodf运算和角度归一化操作，提升了实时控制性能。 refactor(Filter): 改进α-β观测器角度处理精度 修改角度卡尔曼滤波器在归一化角度空间[0,360)内工作，避免大累积角度的浮点精度损失问题，确保静止状态下不会产生虚假速度，同时保持与下游代码的兼容性。 refactor: 为算法模块添加完整文档注释 为所有算法模块(FOC、Filter、pid、thermal)添加了详细的Doxygen文档注释，包括函数说明、参数描述、返回值说明等，便于代码理解和API文档生成。
251 lines
11 KiB
C
251 lines
11 KiB
C
/*!
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\file gd32c10x_exmc.c
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\brief EXMC driver
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\version 2026-01-30, V1.7.0, firmware for GD32C10x
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*/
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/*
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Copyright (c) 2026, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32c10x_exmc.h"
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/* EXMC bank0 register reset value */
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/** @brief BANK0_SNCTL_RESET 宏定义 */
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#define BANK0_SNCTL_RESET ((uint32_t)0x000030DBU)
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/** @brief BANK0_SNTCFG_RESET 宏定义 */
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#define BANK0_SNTCFG_RESET ((uint32_t)0x0FFFFFFFU)
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/** @brief BANK0_SNWTCFG_RESET 宏定义 */
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#define BANK0_SNWTCFG_RESET ((uint32_t)0x0FFFFFFFU)
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/* EXMC register bit offset */
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/** @brief SNCTL_NRMUX_OFFSET 宏定义 */
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#define SNCTL_NRMUX_OFFSET ((uint32_t)1U)
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/** @brief SNCTL_SBRSTEN_OFFSET 宏定义 */
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#define SNCTL_SBRSTEN_OFFSET ((uint32_t)8U)
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/** @brief SNCTL_WRAPEN_OFFSET 宏定义 */
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#define SNCTL_WRAPEN_OFFSET ((uint32_t)10U)
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/** @brief SNCTL_WREN_OFFSET 宏定义 */
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#define SNCTL_WREN_OFFSET ((uint32_t)12U)
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/** @brief SNCTL_NRWTEN_OFFSET 宏定义 */
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#define SNCTL_NRWTEN_OFFSET ((uint32_t)13U)
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/** @brief SNCTL_EXMODEN_OFFSET 宏定义 */
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#define SNCTL_EXMODEN_OFFSET ((uint32_t)14U)
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/** @brief SNCTL_ASYNCWAIT_OFFSET 宏定义 */
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#define SNCTL_ASYNCWAIT_OFFSET ((uint32_t)15U)
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/** @brief SNTCFG_AHLD_OFFSET 宏定义 */
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#define SNTCFG_AHLD_OFFSET ((uint32_t)4U)
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/** @brief SNTCFG_DSET_OFFSET 宏定义 */
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#define SNTCFG_DSET_OFFSET ((uint32_t)8U)
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/** @brief SNTCFG_BUSLAT_OFFSET 宏定义 */
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#define SNTCFG_BUSLAT_OFFSET ((uint32_t)16U)
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/** @brief SNWTCFG_WAHLD_OFFSET 宏定义 */
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#define SNWTCFG_WAHLD_OFFSET ((uint32_t)4U)
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/** @brief SNWTCFG_WDSET_OFFSET 宏定义 */
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#define SNWTCFG_WDSET_OFFSET ((uint32_t)8U)
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/** @brief SNWTCFG_WBUSLAT_OFFSET 宏定义 */
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#define SNWTCFG_WBUSLAT_OFFSET ((uint32_t)16U)
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/*!
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\brief deinitialize EXMC NOR/SRAM bank
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\param[in] none
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\param[out] none
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\retval none
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*/
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void exmc_norsram_deinit(void)
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{
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/* reset the registers */
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EXMC_SNCTL = BANK0_SNCTL_RESET;
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EXMC_SNTCFG = BANK0_SNTCFG_RESET;
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EXMC_SNWTCFG = BANK0_SNWTCFG_RESET;
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}
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/*!
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\brief initialize the struct exmc_norsram_parameter_struct
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\param[in] none
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\param[out] exmc_norsram_init_struct: the initialized struct exmc_norsram_parameter_struct pointer
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\retval none
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*/
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void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
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{
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/* configure the structure with default value */
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exmc_norsram_init_struct->address_data_mux = ENABLE;
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exmc_norsram_init_struct->memory_type = EXMC_MEMORY_TYPE_NOR;
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exmc_norsram_init_struct->databus_width = EXMC_NOR_DATABUS_WIDTH_16B;
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exmc_norsram_init_struct->burst_mode = DISABLE;
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exmc_norsram_init_struct->nwait_polarity = EXMC_NWAIT_POLARITY_LOW;
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exmc_norsram_init_struct->wrap_burst_mode = DISABLE;
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exmc_norsram_init_struct->nwait_config = EXMC_NWAIT_CONFIG_BEFORE;
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exmc_norsram_init_struct->memory_write = ENABLE;
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exmc_norsram_init_struct->nwait_signal = ENABLE;
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exmc_norsram_init_struct->extended_mode = DISABLE;
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exmc_norsram_init_struct->asyn_wait = DISABLE;
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exmc_norsram_init_struct->write_mode = EXMC_ASYN_WRITE;
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/* read/write timing configure */
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exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime = 0xFU;
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exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime = 0xFU;
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exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime = 0xFFU;
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exmc_norsram_init_struct->read_write_timing->bus_latency = 0xFU;
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exmc_norsram_init_struct->read_write_timing->syn_clk_division = EXMC_SYN_CLOCK_RATIO_16_CLK;
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exmc_norsram_init_struct->read_write_timing->syn_data_latency = EXMC_DATALAT_17_CLK;
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exmc_norsram_init_struct->read_write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
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/* write timing configure, when extended mode is used */
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exmc_norsram_init_struct->write_timing->asyn_address_setuptime = 0xFU;
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exmc_norsram_init_struct->write_timing->asyn_address_holdtime = 0xFU;
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exmc_norsram_init_struct->write_timing->asyn_data_setuptime = 0xFFU;
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exmc_norsram_init_struct->write_timing->bus_latency = 0xFU;
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exmc_norsram_init_struct->write_timing->asyn_access_mode = EXMC_ACCESS_MODE_A;
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}
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/*!
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\brief initialize EXMC NOR/SRAM bank
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\param[in] exmc_norsram_parameter_struct: configure the EXMC NOR/SRAM parameter
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write_mode: EXMC_ASYN_WRITE,EXMC_SYN_WRITE
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extended_mode: ENABLE or DISABLE
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asyn_wait: ENABLE or DISABLE
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nwait_signal: ENABLE or DISABLE
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memory_write: ENABLE or DISABLE
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nwait_config: EXMC_NWAIT_CONFIG_BEFORE,EXMC_NWAIT_CONFIG_DURING
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wrap_burst_mode: ENABLE or DISABLE
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nwait_polarity: EXMC_NWAIT_POLARITY_LOW,EXMC_NWAIT_POLARITY_HIGH
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burst_mode: ENABLE or DISABLE
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databus_width: EXMC_NOR_DATABUS_WIDTH_8B,EXMC_NOR_DATABUS_WIDTH_16B
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memory_type: EXMC_MEMORY_TYPE_SRAM,EXMC_MEMORY_TYPE_PSRAM,EXMC_MEMORY_TYPE_NOR
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address_data_mux: ENABLE or DISABLE
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read_write_timing: struct exmc_norsram_timing_parameter_struct set the time
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write_timing: struct exmc_norsram_timing_parameter_struct set the time
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\param[out] none
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\retval none
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*/
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/**
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* @brief exmc_norsram_init 函数
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* @param[in] exmc_norsram_init_struct 参数
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* @return void
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*/
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void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct)
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{
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uint32_t snctl = 0x00000000U, sntcfg = 0x00000000U, snwtcfg = 0x00000000U;
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/* get the register value */
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snctl = EXMC_SNCTL;
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/* clear relative bits */
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snctl &= ((uint32_t)~(EXMC_SNCTL_NRMUX | EXMC_SNCTL_NRTP | EXMC_SNCTL_NRW | EXMC_SNCTL_SBRSTEN |
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EXMC_SNCTL_NREN | EXMC_SNCTL_NRWTPOL | EXMC_SNCTL_WRAPEN | EXMC_SNCTL_NRWTCFG |
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EXMC_SNCTL_WREN | EXMC_SNCTL_NRWTEN | EXMC_SNCTL_EXMODEN | EXMC_SNCTL_ASYNCWAIT |
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EXMC_SNCTL_SYNCWR ));
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snctl |= (uint32_t)(exmc_norsram_init_struct->address_data_mux << SNCTL_NRMUX_OFFSET) |
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exmc_norsram_init_struct->memory_type |
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exmc_norsram_init_struct->databus_width |
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(exmc_norsram_init_struct->burst_mode << SNCTL_SBRSTEN_OFFSET) |
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exmc_norsram_init_struct->nwait_polarity |
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(exmc_norsram_init_struct->wrap_burst_mode << SNCTL_WRAPEN_OFFSET) |
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exmc_norsram_init_struct->nwait_config |
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(exmc_norsram_init_struct->memory_write << SNCTL_WREN_OFFSET) |
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(exmc_norsram_init_struct->nwait_signal << SNCTL_NRWTEN_OFFSET) |
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(exmc_norsram_init_struct->extended_mode << SNCTL_EXMODEN_OFFSET) |
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(exmc_norsram_init_struct->asyn_wait << SNCTL_ASYNCWAIT_OFFSET) |
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exmc_norsram_init_struct->write_mode;
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sntcfg = (uint32_t)((exmc_norsram_init_struct->read_write_timing->asyn_address_setuptime - 1U ) & EXMC_SNTCFG_ASET )|
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(((exmc_norsram_init_struct->read_write_timing->asyn_address_holdtime - 1U ) << SNTCFG_AHLD_OFFSET ) & EXMC_SNTCFG_AHLD ) |
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(((exmc_norsram_init_struct->read_write_timing->asyn_data_setuptime - 1U ) << SNTCFG_DSET_OFFSET ) & EXMC_SNTCFG_DSET ) |
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(((exmc_norsram_init_struct->read_write_timing->bus_latency - 1U ) << SNTCFG_BUSLAT_OFFSET ) & EXMC_SNTCFG_BUSLAT )|
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exmc_norsram_init_struct->read_write_timing->syn_clk_division |
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exmc_norsram_init_struct->read_write_timing->syn_data_latency |
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exmc_norsram_init_struct->read_write_timing->asyn_access_mode;
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/* nor flash access enable */
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if(EXMC_MEMORY_TYPE_NOR == exmc_norsram_init_struct->memory_type){
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snctl |= (uint32_t)EXMC_SNCTL_NREN;
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}
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/* extended mode configure */
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if(ENABLE == exmc_norsram_init_struct->extended_mode){
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snwtcfg = (uint32_t)((exmc_norsram_init_struct->write_timing->asyn_address_setuptime - 1U) & EXMC_SNWTCFG_WASET ) |
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(((exmc_norsram_init_struct->write_timing->asyn_address_holdtime -1U ) << SNWTCFG_WAHLD_OFFSET ) & EXMC_SNWTCFG_WAHLD )|
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(((exmc_norsram_init_struct->write_timing->asyn_data_setuptime -1U ) << SNWTCFG_WDSET_OFFSET ) & EXMC_SNWTCFG_WDSET )|
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(((exmc_norsram_init_struct->write_timing->bus_latency - 1U ) << SNWTCFG_WBUSLAT_OFFSET ) & EXMC_SNWTCFG_WBUSLAT ) |
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exmc_norsram_init_struct->write_timing->asyn_access_mode;
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}else{
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snwtcfg = BANK0_SNWTCFG_RESET;
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}
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/* configure the registers */
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EXMC_SNCTL = snctl;
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EXMC_SNTCFG = sntcfg;
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EXMC_SNWTCFG = snwtcfg;
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}
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/*!
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\brief enable EXMC NOR/PSRAM bank
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\param[in] none
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\param[out] none
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\retval none
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*/
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void exmc_norsram_enable(void)
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{
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EXMC_SNCTL |= (uint32_t)EXMC_SNCTL_NRBKEN;
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}
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/*!
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\brief disable EXMC NOR/PSRAM bank
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\param[in] none
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\param[out] none
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\retval none
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*/
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void exmc_norsram_disable(void)
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{
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EXMC_SNCTL &= ~(uint32_t)EXMC_SNCTL_NRBKEN;
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}
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/*!
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\brief configure CRAM page size
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\param[in] page_size: CRAM page size
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only one parameter can be selected which is shown as below:
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\arg EXMC_CRAM_AUTO_SPLIT: the clock is generated only during synchronous access
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\arg EXMC_CRAM_PAGE_SIZE_128_BYTES: page size is 128 bytes
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\arg EXMC_CRAM_PAGE_SIZE_256_BYTES: page size is 256 bytes
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\arg EXMC_CRAM_PAGE_SIZE_512_BYTES: page size is 512 bytes
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\arg EXMC_CRAM_PAGE_SIZE_1024_BYTES: page size is 1024 bytes
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\param[out] none
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\retval none
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*/
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void exmc_norsram_page_size_config(uint32_t page_size)
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{
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/* reset the bits */
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EXMC_SNCTL &= ~EXMC_SNCTL_CPS;
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/* set the CPS bits */
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EXMC_SNCTL |= page_size;
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}
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